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About me

Academic qualifications

  • BEng (Hons) Electronic Engineering (First Class)1993
  • MSc Digital Signal Processing 1995

Industrial and Commercial Experience

  • (Jan - April 1995) Schematic Entry/ Logic Simulation using the Mentor suit of chip design tools to Service Contractual obligations between GEC Plessey Semiconductors and the University of Westminster
  • (Jul 1996- Feb 1997) VHDL coding, Syntheses and Layout using the Mentor suite of chip design tools to service contractual obligations between GEC Plessey Semiconductors and the University of Westminster
  • (Summer 1997) Manually converting schematics to VHDL code, Syntheses and Floor-planning. To evaluate the effectiveness of the chip layout tool EPOCH.

Teaching

Departmental responsibilities

Course Leader for MSc Embedded Systems validated in October 2008

Module Leader for:

  • 3ECEC425 (Real-Time Audio Processing Project)
  • 3ECE514 (Embedded Microprocessor Design Project),
  • 3MMC502 ( Broadcast Media Systems)
  • 3SMT601 ( Video Broadcasting)
  • 3DSP7B5 (Video & Image Processing)

Research

I am interested in the use of embedded microprocessors in modern day electronic products. In particular I have a general interest in microprocessor & memory architectures; common bus protocol and the efficient programming of microprocessors. More specifically I have interest in real-time systems and associated signal processing algorithms, embedded media systems and robotics.

Past research interests have included the implementation, topology, rapid prototyping and long-term analyses and characterisation of both baseband and bandpass Sigma-Delta modulators. In relation to this I have worked on/with Poly-Phase decimation filtering for the measurement of oversampled data converters, arithmetic noise power calculation for IIR filters, VHDL chip design tools, DSP algorithm development, Field Programmable Gate Arrays (FPGA) for fast prototyping and VLSI ASIC design

  • (January 2003) Practical broadcasting, BBC training and Development, Wood Norton
  • (21 -24 Feb 1995)An introduction to Mentor Design Architect and Quicksim II, DRAL, Rutherford Appleton Laboratory, Oxfordshire
  • (23 - 25 May 1995) VHDL language course, Rutherford Appleton laboratory, Microelectronics Support Centre, Chilton, Didcot, Oxfordshire, OX11 0QX
  • (November 1995)IEE Colloquium on Oversampling and Sigma-Delta Strategies for Digital Signal Processing, London
  • (July 1999)Third International IEE conference on Advanced A/D and D/A Conversion Techniques and their Applications, Glasgow