Mr Sevket Cetinsel, UoA 11, ECS
The University of Westminster was one of my top choices because of its professional and experienced teaching staff. I obtained my BEng (Honours) in Electronic Engineering (2008) and MSc in System-on-Chip Design for DSP and Communications (2009) with Distinction, both from the University of Westminster. During my MSc course I developed an interest in ultra-low-power signal processing which eventually led me to undertake research in this field rather than working in industry. Currently I am pursuing my PhD in ultra-low-power signal processing techniques for Global Navigation Satellite Systems. My research aims to minimise the power consumption of portable satellite positioning devices without compromising performance, thereby helping to increase the power efficiency and battery life of these mobile devices.
Delta-Sigma Modulation is a method used in Analog-to-Digital Converters (ADC), which encode high resolution analog signals into much lower resolution digital signals without compromising the quality of the original analog data.
The work presented here uses our patented low-power 3rd order jitter-insensitive CT-delta-sigma modulator coupled with a decimation processor using our proprietary ultra-low-power processor, CULP-DSP, to achieve very high fidelity digital signals with microwatt power consumption. The modulator/decimation filter cascade can be used in mobile phones and other applications requiring all-digital microphones.
My work concentrates on the design and implementation of a Xilinx Spartan 3 FPGA development system and real-time testing of the decimation processing part deploying all-pass based structures to process the bit stream coming from the CT-Delta-Sigma modulator as well as fully measuring and assessing the silicon integrated modulator chip’s performance. The decimation processor chain starts with a slink filter which acts as a co-processor to the CULP-DSP, decimating by a factor of 32 and feeding the data into our CULP-DSP engine in order to decimate the signal deploying a mix of all-pass based poly-phase filters. The results show that the decimation chain processor analyses and delivers the modulator output with a noise floor of -130dBW/Hz, well below the normal requirements for audio applications.
The initial results demonstrate the validity and efficiency of our approach and points to deployment possibilities in numerous real-life applications in ultra-low-power portable systems ranging from the GNSS to the biomedical field.