Ivan Beretta

Lecturer

+44 20 7911 5000 ext 66497
115 New Cavendish Street London W1W 6UW

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Engineering | Department

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2016

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices (2016)
Beretta, I., Rana, V., Akin, A., Nacci, A. A., Sciuto, D. and Atienza, D. 2016. Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices. ACM Transactions on Embedded Computing Systems (TECS) . 15 (3), p. Article No. 44.
Efficient Hardware Design Of Iterative Stencil Loops (2016)
Rana, V., Beretta, I., Bruschi, F., Nacci, A. A., Atienza, D. and Sciuto, D. 2016. Efficient Hardware Design Of Iterative Stencil Loops. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35 (12), pp. 2018-2031.

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